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Texas Instruments /MSP432P4011 /DMA /DMA_ENACLR

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Interpret as DMA_ENACLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CLR_0)CLR

CLR=CLR_0

Description

Channel Enable Clear Register

Fields

CLR

Set the appropriate bit to disable the corresponding DMA channel.

Note: The controller disables a channel, by setting the appropriate

bit, when:

a) it completes the DMA cycle

b) it reads a channel_cfg memory location which has cycle_ctrl =

b000

c) an ERROR occurs on the AHB-Lite bus.

0 (CLR_0): No effect.

Use the DMA_ENASET Register to enable DMA channels.

1 (CLR_1): Disables channel C.

Writing to a bit where a DMA channel is not implemented has no effect.

Links

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Register License

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data